Successive approximation adc

INTRODUCTION

The successive approximation ADC has been the mainstay of data acquisition systems for many

years. Recent design improvements have extended the sampling frequency of these ADCs into

the megahertz region with 18-bit resolution. The Analog Devices PulSAR® family of SAR

ADCs uses internal switched capacitor techniques along with auto calibration and offers 18-bits

at 2 MSPS (AD7641) on CMOS processes without the need for expensive thin-film laser

trimming. At the 16-bit level, the AD7625 (6 MSPS) and AD7626 (10 MSPS) also represent

breakthrough technology.

The basic successive approximation ADC is shown in Figure 1. It performs conversions on

command. In order to process ac signals, SAR ADCs must have an input sample-and-hold (SHA)

to keep the signal constant during the conversion cycle.

On the assertion of the CONVERT START command, the sample-and-hold (SHA) is placed in

the hold mode, and the internal DAC is set to midscale. The comparator determines whether the

SHA output is above or below the DAC output, and the result (bit 1, the most significant bit of

the conversion) is stored in the successive approximation register (SAR). The DAC is then set

either to ¼ scale or ¾ scale (depending on the value of bit 1), and the comparator makes the

decision for bit 2 of the conversion. The result is stored in the register, and the process continues

until all of the bit values have been determined. When all the bits have been set, tested, and reset

or not as appropriate, the contents of the SAR correspond to the value of the analog input, and

the conversion is complete. These bit "tests" form the basis of a serial output version SAR-based

ADC. Note that the acronym "SAR" actually stands for Successive Approximation Register (the

logic block that controls the conversion process), but is universally accepted as the acronym for

the architecture itself.